Field of the Invention
The invention relates to writing circuit and method for an electrically rewritable non-volatile semiconductor memory apparatus (electrically erasable programmable read-only memory (EEPROM)), such as a flash memory, and a non-volatile memory apparatus.
Description of Related Art
A NAND type non-volatile semiconductor memory apparatus is known, wherein a plurality of memory cell transistors (called memory cells hereinafter) are connected in series between the bit line and the source line to form NAND strings, so as to achieve high integration (see Patent Literature 1, for example).
FIG. 1A is a block diagram showing the overall structure of the conventional NAND flash EEPROM. In addition, FIG. 1B is a circuit diagram showing the structure of a memory cell array and a peripheral circuit thereof in FIG. 1A.
In FIG. 1A, the conventional NAND flash EEPROM includes a memory cell array 10, a control circuit 11 controlling an operation thereof, a row decoder 12, a high voltage generation circuit 13, a page buffer circuit 14 including a data rewriting and reading circuit, a column decoder 15, a command register 17, an address register 18, an operation logic controller 19, a data input/output buffer 50, and a data input/output terminal 51.
In the memory cell array 10, as shown in FIG. 1B, sixteen electrically rewritable non-volatile memory cells MC0-MC15 having a stacked-gate structure are connected in series to form a NAND cell unit NU (NU0, NU1, . . . ), for example. A drain side of each NAND cell unit NU is connected to a bit line BL through a selection gate transistor SG1, and a source side is connected to a common source line CELSRC through a selection gate transistor SG2. Control gates of the memory cells MC (e.g. MC0-MC15) arranged in a row direction are jointly connected to a word line WL (e.g. WL0-WL15). Gate electrodes of the selection gate transistors SG1 and SG2 are connected to selection gate lines SGD and SGS disposed in parallel to the word line WL. A range of the memory cells selected by one word line WL is one page serving as a writing and reading unit. One page or a range of several NAND cell units NU, which is an integer multiple of one page, serves as a unit for data erasing, namely, one block. In order to perform data writing and reading by page, the page buffer circuit 14 includes a sense amplifier circuit and a latch circuit (DL, such as latch circuits 14a and 14b respectively including a plurality of latches L1 and L2) disposed corresponding to each bit line.
The memory cell array 10 of FIG. 1B has a simplified structure, in which a plurality of bit lines may share the page buffer. Here, in an operation of writing or reading data, the bit lines selectively connected to the page buffer become the unit of one page. Moreover, FIG. 1B indicates the range of the cell array where data is inputted/outputted from/to one input/output terminal 51. In order for selection of the word line WL and the bit line BL of the memory cell array 10, the row decoder 12 and the column decoder 15 (as shown in FIG. 1A) are respectively disposed. The control circuit 11 performs sequence control of data writing, erasing, and reading. The high voltage generation circuit 13 controlled by the control circuit 11 generates a boosted high voltage or an intermediate voltage for data rewriting, erasing, and reading.
The input/output buffer 50 is used for inputting/outputting data and inputting an address signal. That is, through the input/output buffer 50 and a data signal line 52, data is transmitted between the input/output terminal 51 and the page buffer circuit 14. The address signal inputted from the data input/output terminal 51 is retained by the address register 18 and sent to the row decoder 12 and the column decoder 15 to be decoded. A command of operation control is also inputted from the data input/output terminal 51. The inputted command is decoded and retained in the command register 17, by which the control circuit 11 is controlled. An external control signal, such as a chip enable signal CEB, a command latch enable signal CLE, an address latch enable signal ALE, a writing enable signal WEB, and a reading enable signal REB, is introduced to the operation logic control circuit 19, so as to generate an internal control signal according to an operation mode. The internal control signal is used for control, e.g. data latch or transmission in the input/output buffer 50, and is sent to the control circuit 11 for operation control.
The page buffer circuit 14 includes two latch circuits 14a and 14b and is configured to switch to execute a multi-level operation function and a cache function. That is, when one memory cell stores two-level data of 1 bit, the cache function is provided; and when one memory cell stores four-level data of 2 bits, the multi-level operation function is set or, though limited by the address, the cache function is set valid.
FIG. 1C is a block diagram showing an exemplary structure of the page buffer circuit 14 and a programming end detection circuit 16 in the NAND flash EEPROM of FIG. 1A. In FIG. 1C, the programming end detection circuit 16 detects the end of programming based on a determination control signal from a page buffer PBn (n=0, 1, 2, . . . N, wherein N is a positive integer). The programming (data writing) and verify determination, and counting of fail bits are explained hereinafter.
In the NAND flash EEPROM, data of one page is written into the memory cell at a time. Here, in order to check whether all the bits have been written, a programming verification process (“programming verification” may be called “verification” hereinafter) is applied for each bit. Basically, when all the bits exceed a predetermined threshold voltage Vth, it is deemed that all the bits have passed and are verified. However, in terms of recent flash memories, the bits may be deemed as in the pass status even though a few fail bits exist. This is called “pseudo-pass processing”, which is used for setting “pass” in a user mode. The reason is that the bits are used during the operation based on an error checking and correction (ECC) function, and because of the many bits correctable ECC function, overall, setting a few bits as “pseudo-pass” during data writing would not cause a problem. In addition, when analyzing the programming characteristic or failure, the evaluation may be carried out by increasing or decreasing the number of the “pseudo-pass” bits to shorten the time or improve the efficiency.
FIG. 2 is a circuit diagram showing a specific exemplary structure of the programming end detection circuit 16 of FIG. 1C. In addition, FIG. 3 is a circuit diagram showing an exemplary structure of the page buffer PBn and a programming end determination part 29-n of FIG. 2.
In FIG. 2, a power voltage VDD is grounded through a MOS (Metal-Oxide Semiconductor) transistor 21 and a MOS transistor 22. A connection point of the MOS transistor 21 and the MOS transistor 22 generates a status signal STB, which indicates the pass status, through a signal line A (PBPUP) and an inverter 23, i.e. a signal output line outputting the determination result. A determination enable signal JENB is applied to a gate of the MOS transistor 21, and a determination reset signal JRST is applied to a gate of the MOS transistor 22. The signal line A (PBPUP) is grounded through a MOS transistor TJn connected to each page buffer PBn and a MOS transistor TJEn whose gate is applied with a verification determination control switch signal JDG_SW (n=0, 1, . . . N). The MOS transistors TJn and TJEn constitute the programming end determination part 29-n (n=0, 1, . . . N) and as a whole form the programming end determination circuit 27.
In FIG. 3, the gate of the MOS transistor TJn is connected to a node SLS1 of the latch L1 of the page buffer PBn. The page buffer PBn includes: the latch L1 including two inverters 61 and 62; the latch L2 including two inverters 63 and 64; a verification capacitor 70; a precharging transistor 71; verification transistors 72-74; column gate transistors 81 and 82; transmission switch transistors 83-85, 88, and 89; bit line selection transistors 86 and 87; and a reset transistor 90.
In FIG. 3, two bit lines BLe and BLo are selectively connected to the page buffer PBn. Meanwhile, according to a bit line selection signal BLSE or BLSO, the bit line selection transistor 86 or 87 is turned on, and one of the bit line BLe and the bit line BLo is selectively connected to the page buffer PBn. Moreover, while one of the bit lines is selected, the other bit line in a non-selected state is set to a fixed ground potential or a power voltage potential according to a bit line non-selection signal YBLE or YBLO, thereby reducing the noise between the adjacent bit lines.
The page buffer PBn of FIG. 3 includes the latch L1 and the latch L2. The page buffer PBn mainly helps the reading and writing operations through predetermined operation control. In addition, the latch L2 is a secondary latch circuit that realizes the cache function in a two-level operation, and assists the operation of the page buffer PBn to achieve a multi-level operation when not using the cache function.
The latch L1 is formed by connecting clocked inverters 61 and 62 in reverse parallel. The bit lines BLe and BLo of the memory cell array 10 are connected to a sense node N1 through the transmission switch transistor 85, and the sense node N1 is further connected to a data retention node SLR1 of the latch L1 through the transmission switch transistor 83. The precharging transistor 71 is disposed at the sense node N1. The data retention node SLR1 is connected to a temporary storage node N3 that is for temporarily storing the data of the data retention node SLR1 through the transmission switch transistor 74. The node N3 is connected to the gate of the transistor 72; the drain of the transistor 72 is connected to a voltage V2; the source is connected to the sense node N1 through the switch transistor 73; and the connection or blocking between the sense node N1 and the voltage V2 is controlled according to a gate control voltage REG of the switch transistor 73 and the voltage value of the node N3. Furthermore, the precharging transistor 71 is also connected to the sense node N1 for precharging the bit lines BLe and BLo with the voltage V1. The capacitor 70 for maintaining the voltage level is connected to the sense node N1. Another end of the capacitor 70 is grounded.
Same as the latch L1, the latch L2 is formed by connecting clocked inverters 63 and 64 in reverse parallel. Two data nodes SLR2 and SLS2 of the latch L2 are connected to the data signal line 52 through the column gate transistors 81 and 82 that are controlled according to a column selection signal CSL (e.g. CSL0-CSL511 as shown in FIG. 1B), and the data signal line 52 is connected to the data input/output buffer 50. The node SLR2 is connected to the sense node N1 through the transmission switch transistor 84.
FIG. 1B illustrates the connection relation between the memory cell array 10, the page buffer PBn, and the data input/output buffer 50. A processing unit of reading and writing of the NAND flash EEPROM is the capacity of one page that is simultaneously selected at a certain row address (e.g. 512 bytes). Since there are eight data input/output terminals 51, it is for example 512 bits for one data input/output terminal 51, and FIG. 1B illustrates the structure of the 512 bits.
When writing data to the memory cell, the written data is introduced to the latch L2 from the data signal line 52. In order to start the writing operation, the written data needs to be in the latch L1. Thus, the data retained in the latch L2 is then transmitted to the latch L1. In the reading operation, in order to output the data to the data input/output terminal 51, the read data needs to be in the latch L2. Thus, the data read from the latch L1 needs to be transmitted to latch L2. Therefore, it is configured that the transmission switch transistors 83 and 84 are set to the on state, and the data is transmitted between the latch L1 and the latch L2. Here, the latch circuit as the transmission target is set to an inactive state for data transmission and then restored to an active state for retaining data.
Hereinafter, an operation of the programming end detection circuit 16 of FIG. 2 and FIG. 3 is explained.
First, data “1” is set to the latch L1 of the page buffer PBn corresponding to the memory cell that is not the programming target, and the voltage of the data retention node SLR1 becomes a high level, so as to be excluded from the verification determination process. For the memory cell that is the programming target, when the programming verification fails, in a state of setting data “0” to the latch L1 of the page buffer PBn, the voltage of the data retention node SLR1 becomes a low level. When the programming verification is passed, data “1” is set to the latch L1 of the page buffer PBn, and the voltage of the data retention node SLR1 becomes the high level. The status of the latches L1 is reflected as the on/off state of the MOS transistor TJn and is used for the verification determination process. As shown in FIG. 2, the MOS transistor TJn (n=0, 1, . . . N) is connected to the signal line A (PBPUP) that performs a NOR (Not OR) operation. If the programming for all memory cells of one page ends and all the data retention nodes SLR1 become the high level, all the MOS transistors TJn are turned off. At the moment, the signal line A (PBPUP) becomes the high level and the status signal STB becomes the low level, by which it is known that the programming ends.
Hereinafter, the conventional “pseudo-pass programming” is explained.
FIG. 4 is a circuit diagram showing an exemplary structure of a programming end detection circuit 16A for pseudo-pass determination in the NAND flash EEPROM of FIG. 1A.
On the left side of FIG. 4, the programming end determination circuit 27 including programming end determination parts 29-0-29-N is disposed, and on the signal line A (PBPUP), a drain current n×Id, which is n times the drain current Id, flows through the MOS transistor 24 from the power voltage VDD, wherein n is an integer. The integer n is the number of the circuits 29-n through which the drain current Id flows and is equivalent to the number of the memory cells that have not passed the programming verification. Further, a reference voltage generation circuit 28 on the right side of FIG. 4 includes reference voltage generation parts 29a-0-29a-J and is formed by a plurality of MOS transistors (BFj and BFEj) connected between a signal line A′ (PBREF) and the ground (here, j=0, 1, . . . J; and J is a positive integer). Here, the MOS transistors BF1-BFJ and BFE1-BFEJ are replica circuits. In order that the current Id flowing through the replica circuit MOS transistors BF1-BFJ and BFE1-BFEJ is the same as the drain current Id of the circuit 29, the transistor sizes of the MOS transistors BF1-BFJ and BFE1-BFEJ and the applied voltages are set completely equal. The sizes of the MOS transistors BF0 and BFE0 or the gate voltage is controlled such that the drain current flowing through the MOS transistors BF0 and BFE0 is 0.5×Id. Moreover, in the signal line PBREF, a threshold reference current Iref flows through the MOS transistor 25 from the power voltage VDD. The threshold reference current Iref is a sum of a unit reference current applied by each reference current generation part that respectively includes a pair of MOS transistors (BF0, BFE0; BF1, BFE1; BF2, BFE2; . . . ).
In addition, corresponding to the number n of the turn-on MOS transistors TJn (n=0, 1, . . . N) in the programming end determination circuit 27, while a voltage corresponding to the drain current n×Id flowing through the MOS transistor 24 is applied to an inverted input terminal of a comparator 26, a voltage corresponding to the threshold reference current Iref flowing through the MOS transistor 25 is applied to a non-inverted input terminal of the comparator 26, and the comparator 26 outputs the status signal STB at low level when n×Id<Ire That is, for the MOS transistors BFj and BFEj of a J+1 group through which the threshold reference current Iref flows (j=0, 1, . . . J), when the number N of the memory cells that do not pass the programming verification is smaller than or equal to J (J≧N), the status signal STB becomes the low level and it is determined as “pseudo-pass”. For example, when J=2, the threshold reference current Iref is 2.5×Id (Iref=2.5×Id). Therefore, the drain current N×Id flowing through the programming end determination circuit 27 is pseudo-pass due to N≦2.
FIG. 5 is a flowchart showing a programming pass determination process of the NAND flash EEPROM of FIG. 1A. In FIG. 5, data is loaded first. In Step S2, the data is programmed and then verified in Step S3. In Step S4, if all the memory cells (one page) are “1”, it is determined as “true pass” in Step S5 and the process ends. On the other hand, if the result of Step S4 is “No”, whether it is “time out” or not is determined in Step S6. If the result is “No”, the process returns to Step S2; otherwise, the process moves on to Step S7. In Step S7, whether it is a tolerable error is determined. If the result is “Yes”, the process moves on to Step S8. If “No”, the process moves on to Step S9. In Step S8, it is determined as “pseudo-pass” and the process ends. In Step S9, it is determined as “failure” and the process ends.